| 摘要 |
The present invention relates to a pipeline circuit device having asynchronous clocks. The pipeline circuit device comprises: multiple combinational logic units arranged in series in a pipeline shape; multiple latch units corresponding to the multiple combinational logic units one to one, and delivering data output from a combinational unit of a previous stage to the combinational logic unit of the next stage between the multiple combinational logic units according to input clock signals, and multiple clock providing units corresponding to the multiple latch units one to one so as to asynchronously provide the clock signals to the multiple latch units. According to the present invention, an asynchronous pipeline-structured circuit may reduce power consumption as compared with a corresponding synchronous pipeline-structured circuit, and the asynchronous pipeline-structured circuit of the present invention may reduce the power consumption further in case of burst-data processing operation as compared with the corresponding synchronous pipeline-structured circuit. |
