ADAPTIVE MICROPROCESSOR POWER RAMP CONTROL

摘要

Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

主权项

1. A system for adaptive self-control of microprocessor power, the system comprising:
a power monitor subsystem disposed to compute a present core power and a present power ramp condition in the microprocessor; a trigger monitor subsystem disposed to determine a control mode corresponding to a likelihood of an imminent power ramp event according to the present core power and the present power ramp condition; and a stall control subsystem disposed to generate a stall control signal as a function of the control mode, the stall control signal operable to stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern.