| 摘要 |
In general, embodiments of the present invention provide a double data rate (DDR) controller unit having a shared address and separate data error correction for DDR3 direct memory access (DMA). In a typical embodiment, the architecture described herein comprises a fields programmable gate array (FPGA) having one memory controller coupled to a data multiplexer (MUX). Memory groups/sets having individual DIMMs are coupled to the memory controller and the data MUX. Data flows between the DIMMs and the data multiplexer, while address and control information flows between the DIMMs and the memory controller. |
