发明名称 VIRTUALIZATION OF MEMORY FOR PROGRAMMABLE LOGIC
摘要 A processing sub-system is configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program. A programmable logic sub-system is configured to implement a set of I/O circuits specified in a configuration data stream, each of the I/O circuits having a respective ID and configured to access one of the variables. A memory management circuit is configured to map the virtual memory addresses to physical memory addresses of a memory and map IDs to the physical address used to store the corresponding variables. A TLB is configured to receive a memory access request, from the I/O circuits, each request indicating an ID and provide, to the memory, a memory access request indicating the physical memory address that is mapped to the;ID.
申请公布号 US2016048454(A1) 申请公布日期 2016.02.18
申请号 US201414462460 申请日期 2014.08.18
申请人 Xilinx, Inc. 发明人 Ahmad Sagheer
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
主权项 1. An electronic system, comprising: a processing sub-system configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program; a programmable logic sub-system configured to implement a set of circuits specified in a configuration data stream, each of the set of circuits including a plurality of input/output circuits, each input/output circuit having a respective identifier (ID) and configured to access a respective one of the variables; a memory; a memory management circuit configured to: map the set of virtual memory addresses to physical memory addresses of the memory; andfor each of the plurality of input/output circuits, map the ID of the input/output circuit to the physical memory address that is mapped to the virtual memory address of the respective variable that the input/output circuit is configured to access; and at least one translation look-aside buffer (TLB) coupled to at least one input/output circuit of the plurality of input/output circuits, the at least one translation look-aside buffer configured to provide to the memory, in response to receiving a memory access request indicating an ID, a memory access request indicating the physical memory address that is mapped to the ID.
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