ALL DIGITAL PHASE LOCKED LOOP WITH CONFIGURABLE MULTIPLIER HAVING A SELECTABLE BIT SIZE

摘要

An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.

主权项

1. An all digital phase locked loop, comprising:
a time-to-digital converter configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal; and a configurable multiplier coupled with the time-to-digital converter, the configurable multiplier having a selectable bit size, the selectable bit size being based on a defined minimum number of bits to obtain a reciprocal of a variable clock period, the minimum number of bits being based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient, wherein the time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.