主权项 |
1. A chip-on-film package, comprising:
a film substrate comprising an upper surface, a lower surface, and a side having a bending part; a semiconductor chip disposed on the upper surface of the film substrate, the semiconductor chip comprising one or more output terminals and one or more input terminals; one or more first output interconnections formed on the upper surface of the film substrate and extending from the semiconductor chip toward the bending part of the film substrate, at least one of the first output interconnections being coupled to a corresponding output terminal of the semiconductor chip; one or more second output interconnections comprising at least one upper second output interconnection and at least one lower second output interconnection, the at least one upper second output interconnection being formed on the upper surface of the film substrate, and the at least one lower second output interconnection being formed on the lower surface of the film substrate and extending toward the bending part of the film substrate, at least one upper second output interconnection being coupled to a corresponding output terminal of the semiconductor chip and at least one lower second output interconnection being coupled to a corresponding output terminal of the semiconductor chip; one or more input interconnections comprising at least one upper input interconnection and at least one lower input interconnection, the at least one upper input interconnection being formed on the upper surface of the film substrate, and the at least one lower input interconnection being formed on the lower surface of the film substrate and extending in a direction away from the bending part of the film substrate, at least one upper input interconnection being coupled to a corresponding input terminal of the semiconductor chip and at least one lower input interconnection being coupled to a corresponding input terminal of the semiconductor chip; and one or more through-vias formed to pass through the film substrate, one or more first through-vias electrically connecting each upper second output interconnection to a corresponding lower second output interconnection of the one or more second output interconnections, and one or more second through-vias electrically connecting each upper input interconnection to a corresponding lower input interconnection of the one or more input interconnections. |