发明名称 CHIP-ON-FILM PACKAGE HAVING BENDING PART
摘要 A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection.
申请公布号 US2016049356(A1) 申请公布日期 2016.02.18
申请号 US201514714234 申请日期 2015.05.15
申请人 Samsung Electronics Co., Ltd. 发明人 JUNG Jae-Min;HA Jeong-Kyu
分类号 H01L23/498;H01L25/065 主分类号 H01L23/498
代理机构 代理人
主权项 1. A chip-on-film package, comprising: a film substrate comprising an upper surface, a lower surface, and a side having a bending part; a semiconductor chip disposed on the upper surface of the film substrate, the semiconductor chip comprising one or more output terminals and one or more input terminals; one or more first output interconnections formed on the upper surface of the film substrate and extending from the semiconductor chip toward the bending part of the film substrate, at least one of the first output interconnections being coupled to a corresponding output terminal of the semiconductor chip; one or more second output interconnections comprising at least one upper second output interconnection and at least one lower second output interconnection, the at least one upper second output interconnection being formed on the upper surface of the film substrate, and the at least one lower second output interconnection being formed on the lower surface of the film substrate and extending toward the bending part of the film substrate, at least one upper second output interconnection being coupled to a corresponding output terminal of the semiconductor chip and at least one lower second output interconnection being coupled to a corresponding output terminal of the semiconductor chip; one or more input interconnections comprising at least one upper input interconnection and at least one lower input interconnection, the at least one upper input interconnection being formed on the upper surface of the film substrate, and the at least one lower input interconnection being formed on the lower surface of the film substrate and extending in a direction away from the bending part of the film substrate, at least one upper input interconnection being coupled to a corresponding input terminal of the semiconductor chip and at least one lower input interconnection being coupled to a corresponding input terminal of the semiconductor chip; and one or more through-vias formed to pass through the film substrate, one or more first through-vias electrically connecting each upper second output interconnection to a corresponding lower second output interconnection of the one or more second output interconnections, and one or more second through-vias electrically connecting each upper input interconnection to a corresponding lower input interconnection of the one or more input interconnections.
地址 Suwon-si KR