VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION

摘要

A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

主权项

1. A method, comprising:
erasing a first erase block of vertical gate stacked NAND memory strings in a first memory array block comprising a plurality of separately erasable erase blocks sharing a common set of word lines by selectively applying a first erase voltage to only a first source line structure connected to the first erase block of vertical gate stacked NAND memory strings.