发明名称 |
SYSTEM AND METHOD FOR CALIBRATION OF A MEMORY INTERFACE |
摘要 |
A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments. |
申请公布号 |
US2016048334(A1) |
申请公布日期 |
2016.02.18 |
申请号 |
US201414461865 |
申请日期 |
2014.08.18 |
申请人 |
Apple Inc. |
发明人 |
Jeter Robert E. |
分类号 |
G06F3/06 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
|
主权项 |
1. A system comprising:
a memory unit including one or more storage arrays; a memory interface unit coupled between a memory controller and the memory unit, wherein the memory interface unit includes:
a timing unit configured to generate timing signals for controlling read and write access to the memory unit; anda control unit configured to calibrate the timing unit at predetermined intervals; and wherein in response to an occurrence of a given predetermined interval, the control unit is configured to calibrate the timing unit using a plurality of partial calibration segments. |
地址 |
Cupertino CA US |