| 发明名称 |
INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS |
| 摘要 |
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow. |
| 申请公布号 |
US2016049371(A1) |
申请公布日期 |
2016.02.18 |
| 申请号 |
US201314779022 |
申请日期 |
2013.06.29 |
| 申请人 |
INTEL CORPORATION |
发明人 |
Lee Kevin J.;Jeong James Y.;Chang Hsiao-Kang;Muirhead John;Telang Adwait;Puri Puneesh;Kang Jiho;Patel Nitin M. |
| 分类号 |
H01L23/538;H01L21/768;H01L23/31;H01L23/00 |
主分类号 |
H01L23/538 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An interconnect apparatus comprising:
a semiconductor substrate having a front and back surfaces; a via extending from the front surface to the back surface; a redistribution layer (RDL) formed over the back surface and the via; and a first passivation layer directly contacting a side surface of the RDL. |
| 地址 |
Santa Clara CA US |
