发明名称 |
MEMORY CELL HAVING ISOLATED CHARGE SITES AND METHOD OF FABRICATING SAME |
摘要 |
Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer. |
申请公布号 |
US2016049418(A1) |
申请公布日期 |
2016.02.18 |
申请号 |
US201314779938 |
申请日期 |
2013.06.25 |
申请人 |
INTEL CORPORATION |
发明人 |
CHANG TING;JAN CHIA-HONG;HAFEZ WALID M. |
分类号 |
H01L27/115;H01L29/792;H01L29/423;H01L29/66;H01L21/28 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A nonvolatile charge trap memory device, comprising:
a substrate having a channel region, a source region and a drain region; and a gate stack disposed above the substrate, over the channel region, wherein the gate stack comprises:
a tunnel dielectric layer disposed above the channel region;a first charge-trapping region and a second charge-trapping region, the regions disposed above the tunnel dielectric layer and separated by a distance;an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region;a gate dielectric layer disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer; anda gate electrode disposed above the gate dielectric layer. |
地址 |
Santa Clara CA US |