| 发明名称 |
MEMORY DEVICE HAVING A SHAREABLE ERROR CORRECTION CODE CELL ARRAY |
| 摘要 |
A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array. |
| 申请公布号 |
US2016048425(A1) |
申请公布日期 |
2016.02.18 |
| 申请号 |
US201514722823 |
申请日期 |
2015.05.27 |
| 申请人 |
Kim Hyun-joong;Kim Soo-hyeong;Shin Sang-hoon;Jung Ju-yun;Song Ho-young;Sohn Kyo-min;Lee Hae-suk;Jung Bu-il;Jeong Han-vit |
发明人 |
Kim Hyun-joong;Kim Soo-hyeong;Shin Sang-hoon;Jung Ju-yun;Song Ho-young;Sohn Kyo-min;Lee Hae-suk;Jung Bu-il;Jeong Han-vit |
| 分类号 |
G06F11/10;G11C29/52 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device, comprising:
a memory cell array; an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to the memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal, store the external parity bits in the ECC cell array. |
| 地址 |
Gyeonggi-do KR |
