发明名称 REDUCED MEMORY ITERATIVE DEMODULATION AND DECODING
摘要 A receiver performing iterative demodulation and decoding, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.
申请公布号 EP2985916(A1) 申请公布日期 2016.02.17
申请号 EP20150179282 申请日期 2015.07.31
申请人 NXP B.V. 发明人 ENGIN, NUR
分类号 H03M13/29;H03M7/00;H03M13/37 主分类号 H03M13/29
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