发明名称 多層配線基板の製造方法
摘要 <P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer wiring board which suppresses variations in thickness of chip component connection terminals and thereby improving the connection reliability with chip components. <P>SOLUTION: A multilayer wiring board has a structure that has a substrate main surface and a substrate rear surface and is formed by laminating multiple resin insulation layers 20 to 27 and multiple conductor layers 28. Multiple IC chip connection terminals 41, connecting with IC chips, and multiple capacitor connection terminals 42, connecting with chip capacitors, are provided on the substrate main surface of the multilayer wiring board. In a plating layer formation process, product plating layers 61, which respectively serve as connection terminals 41, 42, are formed on a resin insulation layer 27 that is the outermost layer exposed on the substrate main surface side 31. Further, dummy plating layers 62 are formed around the product plating layers 61. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP5865769(B2) 申请公布日期 2016.02.17
申请号 JP20120092657 申请日期 2012.04.16
申请人 日本特殊陶業株式会社 发明人 前田 真之介;斉木 一;平野 訓
分类号 H05K3/46 主分类号 H05K3/46
代理机构 代理人
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