Test apparatus and test method

摘要

A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.

主权项

1. A test apparatus comprising:
a first pattern generating circuit that generates a vector pattern which specifies a vector of a device under test; a second pattern generating circuit that generates a synchronization pattern required for a clock recovery circuit which has been built into the device under test to maintain a link with an external circuit; a signal generating circuit that generates a gate signal which is asserted during a period of time in which the vector pattern is to be supplied to the device under test; and a selector circuit that receives the vector pattern, the synchronization pattern, and a control signal which specifies a mode, and to operate such that, in a first mode, it outputs the vector pattern during the period of time in which the gate signal is asserted and outputs a fixed output level during a period of time in which the gate signal is negated, and such that, in a second mode, it outputs the vector pattern during the period of time in which the gate signal is asserted and outputs the synchronization pattern during the period of time in which the gate signal is negated.