Memory devices facilitating differing depths of error detection and/or error correction coverage

摘要

Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array.

主权项

1. A memory device, comprising:
a memory array; and a control circuit for managing the memory array; wherein the control circuit is configured to apply a first depth of error detection and/or error correction coverage to detect and/or correct errors in a first portion of the memory array, and to apply a second depth of error detection and/or error correction coverage to detect and/or correct errors in a second portion of the memory array; wherein the first portion of the memory array is different than the second portion of the memory array; wherein the first depth of error detection and/or error correction coverage is different than the second depth of error detection and/or error correction coverage; and wherein the control circuit is further configured to select a depth of error detection and/or error correction coverage to detect and/or correct errors to be applied to a particular portion of the memory array at least in response to an amount of available data storage in an overhead area associated with the particular portion of the memory array without altering a data size of an area covered by any selected depth of error detection and/or error correction coverage.