Nonvolatile semiconductor memory device

摘要

According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.

主权项

1. A nonvolatile semiconductor memory device, comprising:
a plurality of memory strings each including a plurality of memory transistors connected in series; a first transistor having one end connected to one end of one of the memory strings and functioning as a drain side select transistor of the one of the memory strings; a second transistor having one end connected to the other end of the first transistor; a third transistor having one end connected to the other end of the one of the memory strings and functioning as a source side select transistor of the one of the memory strings; a fourth transistor having one end connected to the other end of the third transistor; a bit line connected to the other end of the second transistor; a source line connected to the other end of the fourth transistor; and a control circuit configured to control a state of the memory strings, the first transistor, the second transistor, the third transistor, and the fourth transistor, each of the memory strings comprising: a first semiconductor layer including a first columnar portion extending in a perpendicular direction with respect to a substrate and functioning as a body of the memory transistors; a first charge storage layer surrounding the first columnar portion and changing a threshold voltage of the memory transistors by storing a charge; and a first conductive layer surrounding the first columnar portion with the first charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the memory transistors, and the first through fourth transistors each comprising: a second semiconductor layer including a second columnar portion extending in the perpendicular direction with respect to the substrate and functioning as a body of the first through fourth transistors; a second charge storage layer surrounding the second columnar portion and changing a threshold voltage of the first through fourth transistors by storing a charge; and a second conductive layer surrounding the second columnar portion with the second charge storage layer sandwiched therebetween, extending in parallel to the substrate, and functioning as a gate of the first through fourth transistors, wherein in the case of performing an operation for increasing the threshold voltage of the first transistor or the third transistor, the control circuit is configured to apply a first voltage to the bit line, and apply a second voltage greater than the first voltage to a gate of the second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to the second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in the second charge storage layer, and in the case of leaving the threshold voltage of the first transistor or the third transistor unincreased, the control circuit is configured to apply the second voltage to the bit line, and apply the second voltage to the gate of the second transistor, thereby charging the first semiconductor layer and the second semiconductor layer to a certain voltage from the bit line via the second transistor and subsequently render the second transistor in a non-conductive state to maintain the first semiconductor layer and the second semiconductor layer in a floating state, and then, apply the program voltage to the gate of the first transistor or the third transistor to increase a voltage of the second semiconductor layer through coupling, thereby prohibiting storage of charge in the second charge storage layer.