Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation

摘要

A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N

主权项

1. A data processing apparatus comprising:
processing circuitry configured to process data; and control circuitry configured to control said processing circuitry to perform a narrowing-and-rounding arithmetic operation in response to a narrowing-and-rounding arithmetic instruction identifying two operands each comprising at least one W-bit data element, said narrowing-and-rounding arithmetic operation generating a result value comprising at least one X-bit result data element, each X-bit result data element representing a sum or difference of corresponding W-bit data elements of said two operands rounded to an X-bit value, where W and X are integers and W>X; wherein said control circuitry is configured to control said processing circuitry to generate each X-bit result data element of said result value by: (a) performing a plurality of N-bit first stage additions to generate respective N-bit intermediate values by adding or subtracting N-bit portions of said corresponding W-bit data elements, where W=J*N and J>1 and N and J are integers; (b) performing one or more N-bit second stage additions, each second stage addition for converting the N-bit intermediate value generated by a corresponding first stage addition into an N-bit rounded result portion of said X-bit result data element by adding a rounding value and a carry value representing a carry output of a preceding first stage addition for adding less significant N-bit portions of said corresponding W-bit data elements than said corresponding first stage addition; and (c) forming said X-bit result data element from the N-bit result portion generated by at least one of said one or more N-bit second stage additions.