| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a voltage spike at clock phase switching and increase the rate of convergence of an output voltage. <P>SOLUTION: First and second common mode voltage detectors 301, 302 are driven by a two-phase clock with non-overlap periods set. The first common mode voltage detector 301 charges in a first clock phase, and generates an output common mode voltage and holds a charge in a second clock phase. The second common mode voltage detector 302 charges in the second clock phase, and generates an output common mode voltage and holds a charge in the first clock phase. In the non-overlap periods, the first and second common mode voltage detectors 301, 302 are electrically isolated from input and output stages by switches 35a-35f, 36a-36f, and a gate-source parasitic capacitance of common mode voltage output transistors holds a charge. <P>COPYRIGHT: (C)2013,JPO&INPIT |
