Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology

摘要

A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

主权项

1. A circuit, comprising:
a first system including a drive circuit configured to generate a first digital signal having a first logic state and a second logic state referenced, respectively, to a first high voltage and a first low voltage of a first supply domain; a second system including a buffer circuit configured to receive the first digital signal and generate a second digital signal having a first logic state and a second logic state referenced, respectively, to a second high voltage and a second low voltage of a second supply domain; wherein the second high voltage is greater than the first high voltage; and wherein the buffer circuit comprises:
a first inverter circuit including a p-channel MOSFET having a gate terminal configured to receive the first digital signal and a transistor body;a second inverter having an input coupled to an output of the first inverter circuit and having an output configured to generate the second digital signal; anda feedback circuit configured to apply the output signal as a bias to the transistor body of the p-channel MOSFET of the first inverter circuit.