Method for integrated circuit manufacturing

摘要

Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

主权项

1. A method comprising:
receiving a design layout of an integrated circuit (IC), wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern; dividing the IC regions into a plurality of groups based on a location effect analysis to the IC design layout such that all IC regions in each of the groups have substantially a same location effect; performing a correction process to the IC design layout using a correction model that includes location effect thereby resulting in a corrected IC design layout, wherein the correction process includes:
performing a first correction to a first IC region in one of the groups, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region;copying the first corrected IC pattern to other IC regions in the respective one of the groups, thereby replacing the initial IC pattern in the other IC regions with the first corrected IC pattern; andrepeating the performing the first correction step and the copying step for each of the groups; and storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.