Automated semiconductor design flaw detection system

摘要

A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.

主权项

1. A design under test verification system comprising:
a simulator operative to implement a first component in hardware description language (HDL), wherein said first component corresponds to said design under test, wherein said first component is operative to convert a value from a register transfer level model into an input value in HDL; an interface component coupled to said simulator and operative to communicate said input value to a second component via a conversion module that converts said input value in HDL into an input signal for said second component, wherein said second component comprises an integrated circuit that is implementing said design under test, wherein said second component is operative to generate a first output value based on said input signal, wherein said conversion module comprises a queuing system that captures and sequences trigger signals comprising asynchronous signals and clock signals, said queuing system comprising a plurality of queues that hold an index for each of said trigger signals, a vector mask for each of said trigger signals, a value to which each of said trigger signals transitions, and values of non-trigger signals, and wherein said first component is further operative to generate a second output value using inputs and outputs from said integrated circuit, and wherein said simulator is further operative to perform a comparison of said first output value and said second output value to verify operation of said integrated circuit against operation of said first component.