Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance

摘要

Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

主权项

1. A semiconductor device comprising:
a junction FET (field-effect transistor) of a normally-on type formed of a substance having a band gap larger than that of silicon and having a first gate electrode, a first source, and a first drain; and a MOSFET (metal-oxide semiconductor FET) of a normally-off type formed of silicon and having a second gate electrode, a second source, and a second drain, the semiconductor device including a cascode connection in which the first source of the junction FET and the second drain of the MOSFET being electrically connected and the first gate electrode of the junction FET and the second source of the MOSFET being electrically connected, and the semiconductor device comprising: (a) a first semiconductor chip having a first front surface in which a first source pad electrically connected to the first source of the junction FET and a first gate pad electrically connected to the first gate electrode of the junction FET are formed and a first back surface electrically connected to the first drain of the junction FET and opposite to the first front surface; (b) a second semiconductor chip having a second front surface in which a second source pad electrically connected to the second source of the MOSFET and a second gate pad electrically connected to the second gate electrode of the MOSFET are formed and a second back surface electrically connected to the second drain of the MOSFET and opposite to the second front surface; (c) a first chip mount unit having a first upper surface on which the first semiconductor chip is mounted via a first conductive adhesive material; (d) a drain lead coupled to the first chip mount unit; (e) a source lead electrically insulated from the drain lead; (f) a gate lead electrically insulated from the drain lead and the source lead; (g) a first metal conductor for electrically connecting the first gate pad of the first semiconductor chip and the source lead together; and (h) a sealing body which seals the first semiconductor chip, the second semiconductor chip, part of the first chip mount unit, part of the drain lead, part of the source lead, and part of the gate lead, and the first metal conductor, wherein the first source pad of the first semiconductor chip and the second back surface of the second semiconductor chip are electrically connected together, the second gate pad of the second semiconductor chip and the gate lead are electrically connected together, the second source pad of the second semiconductor chip and the source lead are electrically connected together, and the first gate pad of the first semiconductor chip are disposed so as to be closer to the source lead than to other leads.