| 摘要 |
Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate. |
| 主权项 |
1. A method of modifying a data rate used in communications between a first processor and a second processor via a bus, the method comprising:
sending, from the first processor, a first handshake signal to the second processor via the bus; receiving, by the second processor, the first handshake signal from the first processor via the bus; sending, from the second processor, a second handshake signal to the first processor via the bus; receiving, by the first processor, the second handshake signal from the second processor via the bus; determining, by the first processor, based on the received second handshake signal, that the second processor is capable of transmitting data via the bus at a first modified data rate; determining, by the second processor, based on the received first handshake signal, that the first processor is capable of transmitting data via the bus at a second modified data rate; instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data via the bus to the first modified data rate; instructing, by the second processor, the first processor to change a data rate at which the first processor transmits data via the bus to the second modified data rate; changing, by the first processor, based on the received instruction from the second processor, the data rate at which the first processor transmits data via the bus to the second modified data rate; and changing, by the second processor, based on the received instruction from the first processor, the data rate at which the second processor transmits data via the bus to the first modified data rate. |
