Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

摘要

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.

主权项

1. A method of forming a plurality of ferroelectric field effect transistors, comprising:
forming a plurality of trenches into semiconductive material, the trenches being parallel and longitudinally elongated relative to horizontal; forming inner dielectric over sidewalls of the trenches and over semiconductive material that is between the trenches; forming first inner conductive material over the inner dielectric, bases of the trenches, the trench sidewalls, and the semiconductive material that is between the trenches, the first inner conductive material being continuous within and between the trenches at least in a direction orthogonal to a horizontal longitudinal running direction of the parallel trenches; forming second inner conductive material over and electrically coupled to the first inner conductive material; the second inner conductive material being formed elevationally thicker over the semiconductive material that is between the trenches than any that is formed elevationally centrally over the trench bases; in at least one common etching step, anisotropically etching both:
a) the first inner conductive material from over the trench bases to isolate the first inner conductive material from being continuous over the individual trench bases; andb) the second inner conductive material that is elevationally over the semiconductive material that is between the trenches; after the etching, forming outer ferroelectric material elevationally over the first inner conductive material that is over the semiconductive material that is between the trenches; forming outer conductive material elevationally over the outer ferroelectric material; and forming source/drain regions in the semiconductive material that is between the trenches on opposing sides of the first inner conductive material that overlies the semiconductive material that is between the trenches.