发明名称 |
Method and apparatus for concurrent test of flash memory cores |
摘要 |
An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access. |
申请公布号 |
US9263147(B2) |
申请公布日期 |
2016.02.16 |
申请号 |
US201414490170 |
申请日期 |
2014.09.18 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Mehrotra Rajat;Parekhji Rubin Ajit;Jalasutram Maheedhar;Shrimali Charu |
分类号 |
G11C16/04;G11C16/34;G11C16/14;G11C29/12;G11C16/16;G11C16/10;G11C16/26;G11C16/08 |
主分类号 |
G11C16/04 |
代理机构 |
|
代理人 |
Pessetto John;Cimino Frank D. |
主权项 |
1. An apparatus for concurrent test of a set of flash memory banks, comprising:
a memory data path module coupled to a test controller, the test controller being configured to generate a test stimulus and to check a response from the set of flash memory banks, the memory data path module comprising: a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; a set of comparators, corresponding to each of the set of flash memory banks, each comparator configured to generate a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks that indicates a state of the set of flash memory banks; a reduction logic configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed to match the width of a data bus of the test controller; a control logic configured to generate a control output in response to the test stimulus and the comparator output for selective programming across different flash bits of the set of flash memory banks; and a fail flag configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read from the set of flash memory banks in any access. |
地址 |
Dallas TX US |