| 摘要 |
A method for designing a PLL or CDR circuit, either of which may contain a loop with a voltage controlled oscillator or other frequency controlled source. For each of a set of values of a gain parameter and a first capacitor of the loop filter of this loop, an analytic solution is employed to find a value for a resistor and a second capacitor of the loop filter. Values of the resistor and the second capacitor which meet a design criterion are selected from among the calculated values. |
