发明名称 Product comprised of FinFET devices with single diffusion break isolation structures
摘要 An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.
申请公布号 US9263516(B1) 申请公布日期 2016.02.16
申请号 US201514823319 申请日期 2015.08.11
申请人 GLOBALFOUNDRIES Inc. 发明人 Wu Xusheng;Xiao Changyong;He Wanxun;Shen Hongliang
分类号 H01L21/84;H01L21/00;H01L29/66;H01L29/06;H01L27/088 主分类号 H01L21/84
代理机构 Amerson Law Firm, PLLC 代理人 Amerson Law Firm, PLLC
主权项 1. An integrated circuit product, comprising: a plurality of trenches in a semiconducting substrate that define first, second and third fins in said substrate, wherein said first, second and third fins are positioned side-by-side, and wherein said second fin is positioned between said first and third fins; a layer of insulating material positioned in said plurality of trenches such that a desired height of said first, second and third fins is positioned above an upper surface of said layer of insulating material; a recess defined in said second fin structure that at least partially defines a cavity in said layer of insulating material; an SDB isolation structure positioned in said cavity on said recessed portion of said second fin, wherein said SDB isolation structure has an upper surface that is positioned at a level that is above a level of said upper surface of said layer of insulating material; and a gate structure for a transistor positioned above said SDB isolation structure.
地址 Grand Cayman KY