发明名称 Semiconductor device with via bar
摘要 A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of the memory die extending over the first surface of the logic die, such that the logic die and the memory die are vertically staggered, and the memory die electrically coupled to the logic die through the via bar. The via bar can be formed from glass, and include through-glass vias (TGVs) and embedded passives such as resistors, capacitors, and inductors. The semiconductor device can be formed as a single package or a package-on-package structure with the via bar and the memory die encapsulated in a package and the substrate and logic die in another package.
申请公布号 US9263370(B2) 申请公布日期 2016.02.16
申请号 US201314040223 申请日期 2013.09.27
申请人 QUALCOMM MEMS Technologies, Inc. 发明人 Shenoy Ravindra Vaman;Lai Kwan-yu;Lasiter Jon Bradley;Stephanou Philip Jason;Kidwell, Jr. Donald William;Gousev Evgeni
分类号 H01L23/48;H01L23/52;H01L29/40;H01L25/065;H01L27/108;H01L23/15;H01L23/498;H01L25/10;H01L25/18;H01L23/50;H01L21/48;H01L23/538 主分类号 H01L23/48
代理机构 Weaver Austin Villeneuve & Sampson, LLP 代理人 Weaver Austin Villeneuve & Sampson, LLP
主权项 1. A device comprising: a second surface of a logic die, a second surface of a first glass via bar, and a second surface of a second glass via bar coupled to a first surface of a substrate; a second surface of a first memory die coupled to a first surface of the first glass via bar, a second surface of a second memory die coupled to a first surface of the second glass via bar, a portion of the second surface of the first memory die and a portion of the second surface of the second memory die extending over the first surface of the logic die, such that the logic die and the first memory die are vertically staggered and the logic die and the second memory die are vertically staggered; and the first memory die electrically coupled to the logic die through the first glass via bar and the second memory die electrically coupled to the logic die through the second glass via bar, and the second memory die electrically coupled to the logic die through the second glass via bar, wherein one or more through-glass vias (TGVs) are formed within the first glass via bar and the second glass via bar.
地址 San Diego CA US