Image display apparatus and method of adjusting clock phase using a delay evaluation signal

摘要

An image display apparatus has an A/D converter for sampling an analog video signal whose signal level changes at a frequency higher than the frequency of a synchronizing signal, based on a reproduced dot clock, and converting the sampled analog video signal into a digital video signal, a clock adjusting circuit for generating a clock in synchronism with the synchronizing signal, delaying the phase of the clock according to set delays, and outputting the delayed clock as the reproduced dot clock, a controller for dividing an area of an image displayed based on the converted digital video signal, into a plurality of image areas defined by display lines in a horizontal direction, and establishing different delays for the divided image areas, and a delay evaluating circuit for converting differential data between adjacent signal levels on the display lines for the respective image areas, into absolute values and accumulatively adding the absolute values, thereby producing accumulated sums. The controller judges the delay established for the divided area with the maximum accumulated sum, as an optimum delay.

主权项

1. An image display apparatus, comprising:
an A/D converter to which an analog video signal whose signal level changes at a constant dot clock that is higher than a frequency of a synchronizing signal representing a display period in a given direction of a displayed image is supplied, said A/D converter sampling the analog video signal based on a supplied reproduced dot clock and converting the sampled analog video signal into a digital video signal; a controller that divides at least a portion of an image displayed based on the digital video signal output from said A/D converter, into a plurality of image areas defined by display lines in said given direction, and establishes different delays for the divided image areas; a clock adjusting circuit that generates a clock in synchronism with said synchronizing signal, delays a phase of the clock according to the delays established by said controller, for respective divided image areas, and outputs the delayed clock as said reproduced dot clock; and a delay evaluating circuit that converts differential data between adjacent signal levels into absolute values and accumulatively adds the absolute values in said given direction based on said reproduced dot clock output from said clock adjusting circuit, with respect to the display lines which define said divided image areas, thereby producing accumulated sums, wherein said analog video signal includes a plurality of analog video signals in respective colors having different wavelengths for respective images to be displayed, wherein said delay evaluating circuit includes a bit shift unit that adds a plurality of digital video signals output from said A/D converter which correspond respectively to said analog video signals, at respective predetermined proportions to generate a delay evaluating signal, and accumulatively adds said differential data for said divided image areas with respect to said delay evaluating signal generated by said bit shift unit, and wherein said controller judges the delay established for the divided image area with a maximum accumulated sum, as an optimum delay.