Device and method for impedance analysis

摘要

An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT.

主权项

1. An impedance analysis device, adapted to on object under test (OUT) and comprising:
a signal generator, configured to supply a pulse signal to the OUT; a signal analysis unit, configured to acquire a response signal which the OUT responds to the pulse signal, and then analyze the response signal to obtain an analysis parameter; and a processing unit, coupled to the signal analysis unit and configured to receive the analysis parameter from the signal analysis unit, so as to obtain an impedance variation characteristic of the OUT; and wherein the signal analysis unit comprises: a buffer unit, configured to receive the response signal to output a buffer signal; a signal amplifying unit, coupled to the buffer unit and configured to amplify a gain of the buffer signal to output an amplified signal; a computing unit, coupled to the signal amplifying unit and configured to receive the amplified signal, and according to the amplified signal and a time difference signal, analyze the response signal to output the analysis parameter; and wherein the computing unit comprises: a first switch having a first end, a second end and a control end, the first end of the first switch receiving the buffer signal, and the control end of the first switch being controlled with a first control signal, so as to control the second end of the first switch to output the buffer signal; a second switch having a first end, a second end and a control end, the first end of the second switch being coupled to the first end of the first switch, and the control end of the second switch being controlled with a second control signal, so as to control the second end of the second switch to output the buffer signal; a capacitor having a first end and a second end, and the first end of the capacitor being coupled to the second end of the first switch and the second end of the second switch; a third switch having a first end, a second end and a control end, the first end of the third switch being coupled to the second end of the capacitor, the second end of the third switch being grounded, and the control end of the third switch being controlled with the first control signal, so as to couple the first end of the third switch to the second end of the third switch; a fourth switch having a first end, a second end and a control end, the first end of the fourth switch being coupled to the second end of the capacitor, and the control end of the fourth switch being controlled with the first control signal, so as to couple the first end of the fourth switch to the second end of the fourth switch; a subtracter having a first input end, a second input end and an output end, the first input end of the subtracter being coupled to the second end of the fourth switch, the output end of the subtracter being coupled to the second input end of the subtracter for outputting a computing signal; a control unit configured to output the first control signal in a first time period, to output the second control signal in a second time period, and to output the time difference signal associated with a difference between the first time period and the second time period, and the first time period preceding the second time period; and a divider coupled to the control unit and the output end of the subtracter and configured to receive the computing signal and the time difference signal and perform division on the computing signal and the time difference signal to generate the analysis parameter.