LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

摘要

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

主权项

1. A circuit element configured to perform a data capture operation, the circuit element comprising:
a first latch element configured to:
receive a first data signal that has a first logic state,invert the first logic state to generate a first inverted logic state, andreceive a first clock signal; and a first logic element coupled to the first latch element and configured to:
invert the first clock signal to generate a first inverted clock signal, andtransmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal.