REPLACEMENT METAL GATE AND FABRICATION PROCESS WITH REDUCED LITHOGRAPHY STEPS

摘要

Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

主权项

1. A method of forming a semiconductor structure, comprising:
forming an nFET short channel trench (SCT), a pFET SCT, an nFET long channel trench (LCT), and a pFET LCT in a dielectric layer that is disposed on a semiconductor substrate; depositing a high-K dielectric layer in the nFET SCT, pFET SCT, nFET LCT, and pFET LCT; depositing an N type work function metal in the nFET SCT, pFET SCT, nFET LCT, and the pFET LCT; performing a high-K dielectric chamfer process on the nFET SCT and pFET SCT; depositing a metal layer in the nFET SCT, pFET SCT, nFET LCT, and the pFET LCT, such that the metal layer is deposited conformally in the nFET LCT and the pFET LCT, and wherein the metal layer fills the nFET SCT and the pFET SCT; depositing a first organic planarization layer in the nFET LCT and the pFET LCT; performing a recess of the metal layer; and depositing a second organic planarization layer in the nFET SCT, pFET SCT, nFET LCT, and the pFET LCT.