Adaptive Selective Bit Line Pre-Charge For Current Savings And Fast Programming

摘要

Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.

主权项

1. A method for operating a memory device, comprising:
applying a program voltage to a word line connected to a set of memory cells in one program-verify iteration of a plurality of program-verify iterations of a programming operation while allowing programming of selected memory cells in the set of memory cells and inhibiting programming of unselected memory cells in the set of memory cells; based on a position of the one program-verify iteration in the plurality of program-verify iterations, determining NS selected target data states, NS is a number>=2, and NU unselected target data states, NU is a number>=1; identify, among the selected memory cells, memory cells which have the NS selected target data states and memory cells which have the NU unselected target data states; and performing a verify portion of the one program-verify iteration, the performing the verify portion comprises applying the number NS of verify voltages to the set of memory cells while sensing the memory cells which have the NS selected target data states and not sensing the memory cells which have the NU unselected target data states, the sensing the memory cells which have the NS selected target data states comprises pre-charging bit lines associated with the memory cells which have the NS selected target data states, and the not sensing the memory cells which have the NU unselected target data states comprises not pre-charging bit lines associated with the memory cells which have the NU unselected target data states.