METHODS AND APPARATUSES INCLUDING A STRING OF MEMORY CELLS HAVING A FIRST SELECT TRANSISTOR COUPLED TO A SECOND SELECT TRANSISTOR

摘要

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

主权项

1. An apparatus comprising:
a data line; a first memory cell; a first select transistor having a gate and being coupled between the data line and the first memory cell; a second memory cell; a second select transistor having a gate; a third select transistor having a gate, wherein the second select transistor is coupled between the second memory cell and the third select transistor, and wherein the third select transistor is coupled between the second select transistor and a source; and a drive transistor having a drain coupled to both:
the gate of the first select transistor; andthe gate of the second select transistor or the gate of the third select transistor.