SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS

摘要

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

主权项

1. An integrated circuit comprising:
(A) a test clock lead, a test mode select lead, a test data in lead, and a test data out lead; (B); a first test access port having a clock input connected to the test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port including topology selection logic, being coupled in a series branch, and having class T0-T3, T4(W), T5(W) capabilities; and (C) a second test access port having a clock input connected to the test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port including topology selection logic, being coupled in a Star-4 branch, having no class T0-T2 capabilities, and having class T3, T4(W), and T5(W) capabilities.