发明名称 |
INSTRUCTION AND LOGIC FOR STORE BROADCAST |
摘要 |
A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor. |
申请公布号 |
US2016041945(A1) |
申请公布日期 |
2016.02.11 |
申请号 |
US201414453341 |
申请日期 |
2014.08.06 |
申请人 |
Intel Corporation |
发明人 |
Mishaeli Michael;Shwartsman Stanislav;Ofir Gal;Kurolap Yulia |
分类号 |
G06F15/78;G06F1/32;G06F9/30 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
|
主权项 |
1. A processor, comprising:
a core including locally-gated circuitry; a decode unit including a first logic to decode a store broadcast instruction of a specified width; a local power gate (LPG) coupled to the locally gated circuitry and including:
a second logic to selectively provide power to the locally-gated circuitry;a third logic to activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations;a fourth logic to deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry an execution unit including a fifth logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor. |
地址 |
Santa Clara CA US |