| 摘要 |
A display has a graphics processor that extracts from image memory just rows that have non-zero luminance information items for the colour under consideration. For each row to be written, the processor sends to a set of N sampling and conversion circuits, at high frequency, a pattern representing the rows to be written, in the form of a succession of N bits. The N samplers successively sample these bits during the succession, to sample and block the bit of rank i in the sampling circuit of rank i, and produce a pattern of N control voltages VGon or VGoff on the rows as a function of the pattern of the received succession, while the graphics processor applies to the columns the luminance data to be written. The operation is repeated solely for the rows that have a luminance information item to be written in the colour under consideration. |
| 主权项 |
1. A matrix liquid crystal display having at least N rows and P columns, and comprising an image memory containing the luminance data for the pixels received for an image to be displayed, including data for each of M rows containing a non-zero image information item, M less than or equal to N, and a graphics processor that is capable of extracting from the memory the addresses of the M rows, and, for each of these, P luminance levels to be applied by P column conductors to the P pixels of the row, with a periodic duration TL for writing a row, and a high-voltage stage having N inputs and having N outputs that are each respectively connected to a respective row conductor that is common to the pixels of one and the same row of the matrix in order to allow the selection of a row of pixels for the purpose of writing luminance data to this row, the display further comprising:
N sampling and conversion circuits having at least one common signal input to be sampled, this input receiving from the graphics processor a pattern of N successive binary words in the course of a duration TL, in which the binary words follow one another at a frequency FH that is equal to at least N/TL, for writing one row among the M rows, and in which the binary word of rank i in the succession has a first value if the row of rank i needs to be written and another value if not, the sampling and conversion circuits having sampling control inputs that are distinct from one another, the output of a sampling and conversion circuit of any rank i being connected to a corresponding input of rank i of the high-voltage stage and supplying this input with a voltage that is dependent on the binary word received, a sampling control circuit that is actuated at the frequency FH in sync with the succession of binary words of rank i=1 to N that are received at the common signal input of the sampling and conversion circuits, the sampling control circuit successively applying a sampling order to each of the N sampling control inputs of the sampling and conversion circuits, so as to sample and convert in the sampling and conversion circuit of rank i the binary word of rank i from the succession of N binary words, a control input of the high-voltage stage in order to apply to the N row conductors voltages corresponding to the voltages that are present on the outputs of the sampling and conversion circuits at the end of reception of the succession of N binary words, and in order to maintain these voltages over a duration that is necessary for writing a row. |
