| 摘要 |
A data processing apparatus and method are provided for communicating between a master device operating from a master clock signal and a slave device operating from a slave clock signal asynchronous to the master clock signal. An interface provides a communication path for the transfer of packets between the master device and the slave device, with the master device initiating transactions where each transaction comprises a plurality of transfers including a master transfer from the master device to the slave device and a slave transfer from the slave device to the master device. A slave clock replica generator associated with the master device generates a slave clock replica that controls timing of transmission of packets by the master device over the interface and timing of reception by the master device of packets sent by the slave device over the interface. In response to a predetermined trigger event, a sync request transfer is issued over the interface from the master device to the slave device, the sync request transfer having a property identifiable by the slave device irrespective of whether the sync request transfer is synchronised with the slave clock signal. In response to a detection of the sync request transfer, the slave device issues over the interface a sync response transfer indicative of at least a frequency of the slave clock signal, and the slave clock replica generator determines at least the frequency of the slave clock replica from that sync response transfer. In addition, the slave clock replica generator references at least a portion of the packet of selected slave transfers in order to determine a phase of the slave clock replica, said at least a portion of the packet containing at least one transition between a first value and a second, different, value. By this approach, determination of the phase of the slave clock replica is decoupled from determination of the frequency of the slave clock replica. |
