发明名称 |
プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
摘要 |
Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ("HLEs"), each of which can provide a portion of the full functionality of an FPGA logic element ("LE"). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. |
申请公布号 |
JP5859089(B2) |
申请公布日期 |
2016.02.10 |
申请号 |
JP20140208874 |
申请日期 |
2014.10.10 |
申请人 |
アルテラ コーポレイションAltera Corporation |
发明人 |
カー ケン チュア;サミー チェウン;ヒー コン プーン;キム ピン タン;ウェイ リァン ゴアイ |
分类号 |
H03K19/173;H03K19/177 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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