发明名称 Conditional notification mechanism
摘要 The described embodiments comprise a computing device with a first processor core and a second processor core. In some embodiments, during operations, the first processor core receives, from the second processor core, an indication of a memory location and a flag. The first processor core then stores the flag in a first cache line in a cache in the first processor core and stores the indication of the memory location separately in a second cache line in the cache. Upon encountering a predetermined result when evaluating a condition for the indicated memory location, the first processor core updates the flag in the first cache line. Based on the update of the flag, the first processor core causes the second processor core to perform an operation.
申请公布号 US9256535(B2) 申请公布日期 2016.02.09
申请号 US201313856728 申请日期 2013.04.04
申请人 ADVANCED MICRO DEVICES, INC. 发明人 Reinhardt Steven K.;Orr Marc S.;Beckmann Bradford M.
分类号 G06F12/00;G06F12/08;G06F13/00;G06F13/28;G06F1/32 主分类号 G06F12/00
代理机构 Park, Vaughan, Fleming & Dowler LLP 代理人 Park, Vaughan, Fleming & Dowler LLP
主权项 1. A method for operating a computing device, comprising: in a first processor core, performing operations for: receiving, from a second processor core, an indication of a memory location, a threshold value to be used when evaluating a condition for the memory location, and a flag;storing the flag in a first cache line in a cache in the first processor core;storing the indication of the memory location and the threshold value in a second cache line in the cache, the second cache line being separate from the first cache line;upon encountering a predetermined result when evaluating the condition for the indicated memory location, updating the flag in the first cache line; andbased on the update of the flag, causing the second processor core to perform an operation.
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