Method and system for inter-processor communication

摘要

A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address.

主权项

1. A system, comprising:
a first distributed computing unit (DCU) comprising:
a first node; anda first DCU master strand (DMS) located on the first node, wherein the first DMS is associated with a first interrupt receive register; a second DCU comprising:
a second node;a global master strand (GMS) located on the second node, wherein the GMS is associated with an interrupt dispatch register; anda DCU global memory comprising first power-on self test (POST) code at a first physical address;wherein the GMS is configured to:
identify the first DMS;determine a first address for the first DMS;determine a payload to transmit to at least the first DMS using at least the first physical address, wherein the payload comprises a sequentially ordered set of bits, wherein at least two bits in the payload are non-zero;select a first non-zero bit in the payload to send to the first DMS;determine a first bit-location of the first non-zero bit in the payload;program the interrupt dispatch register with the first bit-location to obtain a first programmed interrupt dispatch register;issue a cross-call comprising the first bit-location to the first address for the first DMS using the first programmed interrupt dispatch register;select a second non-zero bit in the payload to send to the first DMS;determine a second bit-location of the second non-zero bit in the payload;program the interrupt dispatch register with the second bit-location to obtain a second programmed interrupt dispatch register;issue a cross-call comprising the second bit-location to the first address for the first DMS using the second programmed interrupt dispatch register;after the first non-zero bit and the second non-zero bit in the payload have been transmitted to the first DMS, program the interrupt dispatch register with a completion vector to obtain a third programmed interrupt dispatch register; andissue a cross-call comprising the completion vector to the first address for the first DMS using the third programmed interrupt dispatch register; wherein the first DMS is configured to:
set the first bit-location in the first interrupt receive register to one;set the second bit-location in the first interrupt receive register to one; andafter receiving the completion vector, use a current state of the first interrupt receive register to determine the first physical address.