Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof

摘要

Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

主权项

1. A method for fabricating a Fan-Out Wafer Level Package (FO-WLP), comprising:
electrically coupling an Embedded Ground Plane (EGP) to a backside contact of a first microelectronic device through a backside EGP interconnect structure; electrically coupling the backside EGP interconnect structure between the EGP and a backside contact of a second microelectronic device; forming a molded package body around the first microelectronic device, the second microelectronic device, the EGP, and the backside EGP interconnect structure, the molded package body having a frontside at which the EGP is exposed; and producing one or more Redistribution Layers (RDLs) over the frontside of the molded packaged body, the one or more RDLs containing at least one interconnect line electrically coupled to the backside contact of the first microelectronic device through the EGP and the backside EGP interconnect structure.