发明名称 |
Memory module architecture |
摘要 |
In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments. |
申请公布号 |
US9256493(B2) |
申请公布日期 |
2016.02.09 |
申请号 |
US201113993506 |
申请日期 |
2011.12.28 |
申请人 |
Intel Corporation |
发明人 |
Nachimuthu Murugasamy K.;Kumar Mohan J.;Das Debaleena;Ziakas Dimitrios |
分类号 |
G06F11/10;G11C5/04;G11C13/00 |
主分类号 |
G06F11/10 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A method comprising:
enabling a dual in line memory module including a plurality of memory integrated circuits to store data with error correcting code on each of said memory integrated circuits. |
地址 |
Santa Clara CA US |