| 摘要 |
Each unit among a pipeline of image processing units receives a new configuration vector (update), and the received new vector is only applied in sync with the Timing-derived trigger signal within a hardware-enabled time period. A hardware enable signal is logically combined with a Timing-derived triggering event signal to control a switch that applies the new received vector to the processing unit. This ensures that each image processing unit (stage) in the chain of image processing units is updated in sequence even if the CPU has output the updated configuration vectors independently of the Timing of the Data and without regard for the delay through each of the processing units. The Timing-derived triggering event is used to synchronize the application of a received configuration vector update with the receipt by the unit of a new frame of image DATA. |
