Configurable decoder with applications in FPGAs

摘要

The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x

主权项

1. An apparatus comprising: a circuit having a decoder in combination with a bit-slice mapping unit, where the circuit has as input an x-bit input word having a binary value at each x-bit position, where the x-bit input word is input into the decoder which has a z-bit source word output having binary value at each z-bit position, where the z-bit source word is input into the mapping unit which also receives y-bit selector address input from outside the circuit, where the circuit outputs an(nα)⁢-⁢bitoutput word having a binary value at each(nα)⁢-⁢bitposition,nαbeing an integer and α is an integer ≧2, where n>z>x, where each(nα)⁢-⁢bitposition is hardwire connectable to a subset of said z-bit positions (the “Mapping Subsets”) of the z-bit source word.