Multi-threshold circuitry based on silicon-on-insulator technology

摘要

Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.

主权项

1. An apparatus for digital evaluation comprising:
a plurality of transistors configured to form a logic gate where the plurality of transistors are formed in a silicon-on-insulator (SOI) semiconductor technology, wherein:
the plurality of transistors include a plurality of PFETs;the plurality of transistors include a plurality of NFETs;a first PFET, from the plurality of PFETs, and a first NFET, from the plurality of NFETs, share a first buried well under an insulator in the silicon-on-insulator semiconductor technology;a second PFET, from the plurality of PFETs, and a second NFET, from the plurality of NFETs, share a second buried well under an insulator in the silicon-on-insulator semiconductor technology; anda first connection that biases the first buried well and a second connection that biases the second buried well wherein the first buried well is biased so that the first PFET or the first NFET has a low threshold voltage and the second buried well is biased so that the second PFET or the second NFET has a low threshold voltage.