Method for manufacturing transistor and associated device

摘要

A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

主权项

1. A method for manufacturing a transistor device, comprising:
providing a plurality of parallel nanowires on a substrate, each nanowire having a first end and a second end, wherein the first end and the second end of each nanowire are connected to each other by a connection portion, wherein the plurality of nanowires and the connection portions comprise a same material; providing a dummy gate structure over a central portion of the parallel nanowires, thereby covering the central portion of the parallel nanowires; epitaxially growing extension portions selectively on the parallel nanowires and the connection portions, outside of the central portion of the parallel nanowires, wherein the extension portions comprise a second material; providing a filler layer around and on top of the dummy gate structure and the extension portions; flattening the filler layer, whereby an upper surface of the dummy gate structure is exposed; removing the dummy gate structure, whereby a gate trench is created and whereby the central portion of the parallel nanowires is exposed; providing spacer structures on sidewalls of the gate trench, whereby a final gate trench is defined; thereafter, thinning the parallel nanowires, whereby free space in between the nanowires and the spacer structures is created, resulting in an extended exposed portion of the parallel nanowires; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, whereby a connection between the quantum well layer and respective extension portions is provided.