FinFETs with different fin height and EPI height setting

摘要

An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

主权项

1. A method comprising:
forming a first and a second plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein a first portion of the semiconductor substrate between the first plurality of STI regions is configured as a first semiconductor strip, and a second portion of the semiconductor substrate between the second plurality of STI regions is configured as a second semiconductor strip; recessing the first semiconductor strip to form a first recess having a first depth; performing a first epitaxy to grow a first epitaxy strip in the first recess; recessing the second semiconductor strip to form a second recess having a second depth different from the first depth; performing a second epitaxy to grow a second epitaxy strip in the second recess; and recessing the first plurality of STI regions and the second plurality of STI regions to form a first semiconductor fin and a second semiconductor fin, respectively, wherein the first semiconductor fin comprises a top portion of the first epitaxy strip, and the second semiconductor fin comprises a top portion of the second epitaxy strip.