| 发明名称 | Semiconductor test wafer and methods for use thereof | ||
| 摘要 | A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer. | ||
| 申请公布号 | US9257352(B2) | 申请公布日期 | 2016.02.09 |
| 申请号 | US201313835358 | 申请日期 | 2013.03.15 |
| 申请人 | GlobalFoundries, Inc. | 发明人 | Daubenspeck Timothy H.;Gambino Jeffrey P.;Muzzy Christopher D.;Sauter Wolfgang |
| 分类号 | G01R31/02;G01R31/26;H01L21/66 | 主分类号 | G01R31/02 |
| 代理机构 | Hoffman Warnick LLC | 代理人 | Canale Anthony J.;Hoffman Warnick LLC |
| 主权项 | 1. A test device, comprising: a wafer having a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon, wherein the test structure is configured to facilitate characterization of a critical defect on the second side of the wafer that is caused by any of a plurality of tools used in a wafer manufacturing process, and wherein the test structure is chosen from a group consisting of: a plurality of test structures embedded in the second side of the wafer and a blanket layer of copper embedded in the second side of the wafer. | ||
| 地址 | Grand Cayman KY | ||