| 发明名称 |
Vertical transistor and method to form vertical transistor contact node |
| 摘要 |
A vertical transistor structure includes a substrate with a protruding structure, an offset layer covering a top surface of the protruding structure, a conductive layer disposed on the offset layer, and an interlayer disposed between the offset layer and the conductive layer to serve as a contact node. |
| 申请公布号 |
US9257553(B2) |
申请公布日期 |
2016.02.09 |
| 申请号 |
US201414504385 |
申请日期 |
2014.10.01 |
| 申请人 |
INOTERA MEMORIES, INC. |
发明人 |
Lee Tzung-Han |
| 分类号 |
H01L29/78;H01L29/66 |
主分类号 |
H01L29/78 |
| 代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
| 主权项 |
1. A vertical transistor structure, comprising:
a substrate having a protruding structure; an offset layer covering a top surface of the protruding structure; and an interlayer on the offset layer, wherein the interlayer comprises a composite conductive layer formed from the offset layer and functions as a contact node of the vertical transistor structure, wherein the protruding structure is a cubic shaped structure. |
| 地址 |
Hwa-Ya Technology Park Kueishan, Taoyuan TW |
